1. Technical Field
Embodiments of the present disclosure relate to semiconductor devices.
2. Related Art
Semiconductor memory devices, for example, dynamic random access memory (DRAM) devices may have row address paths, column address paths and data paths. The row address path may be created during an operation for selecting a word line using a row address signal supplied from an external device and for amplifying the data stored in at least one memory cell connected to the selected word line using at least one sense amplifier, and the column address path may be created during an operation for selecting one of a plurality of output enable signals using a column address signal. Further, the data path may be created during an operation for transmitting data on bit lines to an external device through input/output (I/O) lines, sense amplifiers and data output buffers, the sense amplifiers and data output buffers. The operation (hereinafter, referred to as a column operation) relating to the column address path may be controlled by a column path circuit which is suitable for including a column decoder. The column path circuit may decode the column address signal to selectively enable any one of the plurality of column selection signals and may transmit the data on the bit line selected by the enabled column selection signal to the I/O line.
In general, the semiconductor device such as the DRAM device may be suitable for including a plurality of memory banks, and each of the memory banks may include a plurality of memory cells. Addresses allocated to the memory cells of one of the memory banks may be identical to addresses allocated to the memory cells of another memory bank. Thus, the semiconductor device may simultaneously output the data of the memory cells that are disposed in respective ones of the memory banks to have the same address. To this end, the column path circuit may decode the column address signals to selectively enable any one of the plurality of column selection signals and may perform the column operation for simultaneously transmitting the data on the bit lines of the memory banks selected by the selected column selection signal to the I/O lines.